Critical path analysis of two-channel interleaved digital MASH ΔΣ modulators
نویسندگان
چکیده
Implementation of wireless wideband transmitters using ∆Σ DACs requires very high speed modulators. Digital MASH ∆Σ modulators are good candidates for speed enhancement using interleaving because they require only adders and can be cascaded. This paper presents an analysis of the integrator critical path of two-channel interleaved ∆Σ modulators. The bottlenecks for a high-speed operation are identified and the performance of different logic styles is compared. Static combinational logic shows the best trade-off and potential for use in such high speed modulators. A prototype 12-bit second order MASH ∆Σ modulator designed in 65 nm CMOS technology based on this study achieves 9 GHz operation at 1 V supply.
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